This application incorporates by reference Taiwanese application Serial No. 90110228, filed on Apr. 27, 2001.
1. Field of the Invention
The invention relates in general to a phase-locked loop, and more particularly to a phase-locked loop with dual-mode phase/frequency detection, which is suitable for use in wireless communication systems.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit, which generates a signal maintaining a constant phase and frequency relative to a reference signal. Phase-locked loops are widely used in wireless communications. For the years, as the wireless communications become more and more important, how to obtain a low-noise, high-speed PLL is an important topic for the industry.
Referring to FIG. 1, it is a block diagram illustrating a conventional PLL. In a wireless communication system, a PLL 100 is to convert an intermediate frequency (IF) signal into a radio frequency (RF) signal. The PLL 100 includes a phase/frequency detector (PFD) 102, a loop filter (LP) 104, a voltage-controlled oscillator (VCO) 106, and a frequency converter 110. The PFD 102 receives an input frequency fIF and a reference frequency fref, and compares the input frequency fIF with the reference frequency fref so as to obtain an output signal S1 proportional to the phase difference between the input frequency fIF and the reference frequency fref. After the LP 104 filters the output signal S1 for removing undesired high-frequency components and noise from the output signal S1, the LP 104 outputs an output signal S2. The output signal S2 is then as an input to the VCO 106. The VCO 106 outputs an output frequency fRF as an output of the PLL 100. Besides, the output frequency fRF is fed into the frequency converter 110 through a coupler 108. The frequency converter 110 outputs a reference frequency fref equal to a local signal frequency fLO minus the output frequency fRF.
After initialization and the operation for a settling time, the PLL 100 enters a lock state in which the reference frequency fref is equal to the input frequency fIF and the output frequency fRF is given by the local signal frequency fLO minus the input frequency fRF.
When the PFD 102 of the PLL 100 is an analog PFD, the PLL 100 has a frequency response as shown in FIG. 2 after initialized. An analog PFD detector can be implemented by an analog multiplier. Besides, an analog PFD is characterized by a lock-in range. As an input to the analog PFD, the reference frequency fref has to be within the lock-in range, such as the range between the frequencies f1 and f2 as shown in FIG. 2, so that the analog PFD operates properly to cause the reference voltage varying as the phase difference between the inputs of the analog PFD. As shown in from FIG. 2, after the PLL 100 is initiated, the reference frequency fref varies for a settling time, and then the reference frequency fref enters the lock-in range while the PLL 100 is in the lock state. Since the lock-in range for an analog PFD is narrow, it takes a long settling time for the PLL 100 from the start of control of the PLL 100 to the lock state. In this way, when the analog PFD is used in a situation where frequency switching is involved, the long settling time results in a low switching speed.
A PLL that has a reduced settling time so as to increase the switching speed is described in U.S. Pat. No. 6,163,585, where a constant current source is used to achieve the reduced settling time. However, for a PLL circuit according to U.S. Pat. No. 6,163,585, the amount of the current from the constant current source must be related to the output current of a phase comparator under a condition, that is, the rate of the former and the latter must be within a specific range. Otherwise, the PLL may not lock in.
On the other hand, if a digital PFD is substituted for the PFD 102 in FIG. 1, the problem of having a long settling time and a low switching time can be avoided. Referring to FIG. 3, it shows a frequency response of the PLL 100 with a digital PFD substituted for the analog one. As the digital PFD is started with the reference frequency fref at an initial frequency f0, it will cause the reference frequency fref, in a short time, to approach the input frequency fIF. Since the lock-in range of a digital PFD is broad, the switching speed of the digital PFD is high. However, compared with the analog PFD, the digital PFD has the disadvantages of lower sensitivity, bad linearity, and the excessive noise in an in-band range. Therefore, the quality of the output signal of the PLL with the digital PFD is degraded.
In order to specify the differences between the conventional analog and digital FPDs, FIGS. 4A and 4B are two diagrams showing the relation between the phase differences and average currents of the output signals of the conventional analogy PFD and the conventional digital PFD respectively. In FIG. 4A, the average output current from the analog PFD, denoted by Iavexe2x80x94A, is fully linearly dependent on the phase difference xcex8 of the input frequency fIF and the reference frequency fref, which corresponds to a straight line LA through the origin O as shown in FIG. 4A. In FIG. 4B, the average output current from the digital PFD, denoted by Iavexe2x80x94D, is partially linearly dependent on the phase difference xcex8 of the input frequency fIF and the reference frequency fref. That is, as shown in FIG. 4B, when the phase difference xcex8 is between xcex81 and xcex82, Iavexe2x80x94D is almost equal to zero. In this way, when the phase difference is a small value, it may occur that the digital PFD cannot discriminate between the phases of the input frequency fIF and the reference frequency fref. Since the analog PFD provides high linearity, the PLL using the analog PFD, as being locked in, obtains the reference frequency fref much more close to the input frequency fIF. Compared with the digital PFD, the analog PFD has lower in-band noise and better sensitivity to phase difference so that the output signal of the PLL at the output frequency fRF has good quality.
Hence, since the digital PFD has the deficient sensitivity to phase difference, the output signal of the PLL with the digital PFD has greater in-band noise than that of the PLL with the analog PFD. Referring to FIG. 5, it shows a frequency spectrum of the output frequency of a conventional PLL with the digital PFD. When the phase difference is in the range from xcex81 to xcex82, the digital PFD is unable to discriminate between its inputs so that the output signal of the PLL using the digital PFD becomes a signal centered at frequency fRF0 with bandwidth between f3 and f4, wherein fRF0 is given by the local signal frequency fLO minus the input frequency fIF. Thus, it results in the degradation of the output signal of the PLL.
It is therefore an object of the invention to provide a phase-locked loop (PLL) circuit with dual-mode phase/frequency detection. By using the PLL with dual-mode phase/frequency detection, the problem that the conventional PLL using an analog phase/frequency detector provides a low switching speed is avoided. In addition, the PLL with dual-mode phase/frequency detection has the advantages of providing linear characteristics, increased switching speed, and high sensitivity.
According to the object of the invention, a phase-locked loop circuit with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. The dual-mode phase/frequency detector is to receive an input frequency and a reference frequency, and to obtain a detection output signal corresponding to the phase difference between the input frequency and the reference frequency. The loop filter is for filtering the detection output signal to output a filtered detection output signal. The voltage-controlled oscillator is coupled to the loop filter and is used for outputting an output frequency according to the filtered detection output signal. The frequency converter is used for receiving the output frequency and outputting the reference frequency, wherein the reference frequency corresponds to the output frequency. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. The digital phase/frequency detector is used for outputting a digital signal according to the input frequency and the reference frequency. The analog phase/frequency detector is used for outputting an analog signal according to the input frequency and the reference frequency. The charge pump is coupled to the digital phase/frequency detector and the analog phase/frequency detector, and is used for outputting the detection output signal corresponding to the phase difference between the input frequency and the reference frequency. The control unit is used for controlling the digital phase/frequency detector and the analog phase/frequency detector. When the phase-locked loop circuit starts, the control unit causes the detection output signal to correspond to the digital signal, and when the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to the analog signal.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings described as follows.